EDN

How to write an optimized FIR filter

Before we show how to optimize a FIR filter, let's review the basics of DSP architectures. (If you are already familiar with these basics, you can skip ahead to the page 2. To learn more about the ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Design-Reuse

Systolic FIR Filter Based FPGA

In this paper, we first review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic ...
Hackaday

FIR filter

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...
Electronic Design

Adding A FIR Filter After An ADC Gets Simpler

The QF1D512 SavFIRe configurable finite impulse response (FIR) filter chip can follow any analog-to-digital converter (ADC) in industrial monitoring applications like vibration sensing, flow ...