Cadence’s Paul McLellan shares highlights from the recent Hot Chips tutorial on CXL and how enhanced memory pooling enables new memory usage models as CXL 3.0 approaches the same speed as DRAM.

Cadence’s Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance. Synopsys’ Om Prakash Thakur and Nusrat ...