EDN

FIFO, handshake synchronizers a challenge for CDC analysis

Among the many verification challenges confronting system-on-chip designers these days, clock domain crossings (CDCs) rank near the top in difficulty. Two particularly troublesome CDC-related issues ...
Design-Reuse

Design Transition from Sync to Async: Design and Verification Challenges

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...
Electronic Design

Clock Domain Crossing and Synchronizers (Part 2): Best Practices

As chip designs grow in complexity and face tighter power constraints, depending on a single clock domain is no longer ...
Embedded

Asynchronous reset synchronization and distribution – challenges and solutions

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...
TechRepublic

Verification of Asynchronous FIFO Using System Verilog

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...
EDN

Getting a handle on CDC analysis

Among the verification challenges confronting system-on-chip designers, clock domain crossings (CDCs) rank near the top in difficulty. CDCs have become a leading cause of design errors. Errors may ...